Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. Dany Lepage discusses the architectural ...

A monthly overview of things you need to know as an architect or aspiring architect. Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with ...

JTAG has its place but it is not by any means the total solution. Boundary scan, as standardized by IEEE 1149.1 and commonly referred to as JTAG, has truly revolutionized the testability of circuit ...

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by ...

Software has typically been developed with three primary considerations in mind: time to market, budget and functionality. The schedule rules, now more than ever; software has become a competitive ...

For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability ...

Atrenta's SpyGlass DFT, an addition to its SpyGlass predictive-analysis tool, helps designers identify at the register transfer level (RTL) testability issues that would normally appear only at the ...